In digital communications systems, the transmission of data is subject to corruption and errors due to the presence of noise in the communication channel. Scrambling, used to facilitate accurate reception of the signal at the destination, introduces additional errors through a process known as error spreading. In such systems, it is common to encode the transmitted signal at the source using redundant parity bits to allow correction of the errors. A digital bit stream is typically parsed into fixed length datawords of n bits based on a maximum length for which the system receiver can extract a clock signal timing reference from the transmitted data. With the concatenation of redundant bits the encoded digital word of m bits is longer than the original dataword.
One of the challenges in providing error correction for high-speed links is that any error correcting checkbits appended to the dataword being protected also need to be considered for their effect on the bit transition density of the physical layer. Typically, in order to maintain synchronization with the proper position within a packet boundary to strobe data, a minimum number of transitions from 0=>1 or from 1=>0 must be observed. A long stream of 0's, for example, may cause a receiver to lose track of when to sample the incoming data. Thus when a 1 is ultimately transmitted, the receiver may have lost synchronization and fail to detect the 0=>1 transition.
In order to prevent loss of synchronization, an encoded dataword may be processed by one of several known scrambling techniques. A self-synchronized scrambler is often implemented with a Linear Feedback Shift Register (LFSR) that is programmed to multiply the dataword according to a predefined polynomial to cause a mathematically guaranteed minimum number of bit transitions. The scrambler LFSR can also be preset to a specific value to further enhance the number of bit transitions for an all-zero data payload. On the receiving side, the payload must be descrambled, usually by a similar inverse process, where the bitstream is divided by the same predefined polynomial.
Data scrambling is used to maintain clock synchronization between the transmitter and receiver. For the reasons stated above, data scrambling algorithms usually limit the maximum number of sequentially transmitted ones or zeros, such that a minimum number of logic transitions may be recognized for successful extraction of the transmitted clock. Limiting the maximum number of bits having the same value enables the receiver to maintain synchronization with the source.
Although scrambling is helpful in reducing receiver drift, it provides an additional source of transmission errors because single bit errors occurring in the original data stream are multiplied through the scrambling process. The multiplication of a single bit error occurs because the scrambling and descrambling functions rely on each bit of a dataword, including a bit that is in error when reconstructing the original transmitted data. The multiplication of single bit errors in this fashion is known as “bit error spreading” and occurs at the receiver when a descrambler attempts to restore the scrambled signal to its original state.
In order to insure that all of the bitstream is properly scrambled, any error correcting code (ECC) checkbits appended to the dataword must also be scrambled. This necessitates that scrambling be done after the ECC checkbits are added to the transmitted word. The transmitted dataword is likewise descrambled at the receiver prior to activating whatever ECC scheme is implemented in the receiver. In this manner, the bit transmission density is maintained for the entire packet, and not just the databit portion of the packet.
An exemplar prior art communications system is shown in FIG. 1, wherein (Physical Coding Sublayer) upper interface 100 represents a 10 gigabit media independent interface (XGMII) that provides an interface for data communications equipment irrespective of the physical mode of transport of data to be forwarded 102 or received 104. The encoder 142 and gear box 146 functions are necessary to map data and control character to the blocks and to adapt formats. They are not necessary to the understanding of the invention and are not further described. Receive path 150 includes the descrambler 154 to recover the original stream of bits. PCS 120 also includes a function 160 to monitor bit error rate over the transmission medium and there is a decode function 152 which is the counterpart of the transmit encoder 142. Data from a logical interface 100 is sent to the physical coding sublayer 120, where first it is encoded with an appropriate ECC and then scrambled. Finally, if necessary, the speed of the logic circuits performing the encoding and scrambling is matched to the transmission speed of the actual physical medium 115 by gearbox 146. In the case of the 64B/66B code, as the name suggests, two bits are added by the gearbox for every 64 bits to be transmitted. The two extra bits, used to frame the 64-bit packets, are removed at reception and are not included in the scrambling and correction processing steps. The data is then sent across the interface medium as a packet containing the original dataword plus the encoded checkbits, all of which have been scrambled to provide the required bit transition density.
Those skilled in the art will realize that although the invention is described in the particular context of 10GbE it could be practiced as well in a different environment and will know, from the detailed description infra, how to adapt it to other applications especially, for applications where a different scrambling polynomial would be used.
During the physical transmission of the payload, random, single-bit errors are common. This is due to the extremely high speeds employed in communications channels used today. If there were only one error in the data packet, then a simple Hamming ECC would be able to correct all such errors. Because self-synchronized scramblers multiply errors, a more robust solution is required at the receiver to handle the incident error and any replicated errors.
On the receiving end, which could be in the same logic chip or on a completely different logic chip, the received packet is first synchronized and the packet boundaries detected. The invention does not assume any particular method for delineating packet boundaries. Often, when fixed size packets are transmitted, packet boundaries are detected on the basis of the added redundant bits and encoding of the data stream. Then, in order to keep the bit error rate (BER) as low as possible, the packet is received using a predefined bit transition density derived from the scrambling step. The received packet is descrambled and then decoded to allow for the correction of any errors in the bit stream.
However, as mentioned above, the descrambling process has the undesirable effect of causing any single-bit errors that were introduced in the channel during transmission to be replicated according to the number of terms and degree of the scrambling polynomial. A single bit error can simply be propagated across the channel, or it may be replicated multiple times depending on the form of the scrambling polynomial. Whether the error remains a single-bit error or is replicated multiple times depends on where in the transmitted payload sequence it occurs. If the error occurs at the beginning of the sequence, then it will be spread as a result of the LFSR and will usually be replicated within the same data packet, provided the highest order of the polynomial is less than the total number of bits in the transmitted sequence. If the initial error occurs towards the end of the payload, it will still be spread, however, only the first occurrence may fall in the current packet, leading to only a single bit error. Nonetheless, the replicated manifestations of the error will then fall into the next data packet and cause a double-bit error there. Incident errors in the middle of the word can be spread into various double-bit errors, according to the scrambling polynomial and the position of the incident error.
Another aspect of digital communications related to bit transition density or maximum run length is cumulative DC offset, which reflects the sum of the low frequency voltage components of the transmitted data stream experienced at the receiver. In binary systems, discrete logic values for zero and one are typically assigned opposite polarity voltages. As a result, without periodic adjustment, the cumulative DC offset experienced at the receiver can migrate toward the positive or negative power supply limit, which may lead to an overload condition at the receiver. The cumulative DC imbalance can be expressed as the number of bit values required to be inverted to produce a balanced bit stream. If the cumulative DC offset experienced at the receiver can be effectively balanced, the DC voltage swing experienced at the receiver can be reduced. In this regard, a balanced DC offset can be exploited to reduce overall signal to noise ratio (SNR) at the receiver because low frequency noise may be more effectively filtered out. This is accomplished by ensuring the encoded data stream represents a balanced distribution of logic zero and one values over a fixed unit of data bits.
Forward error correction (FEC) is a technique designed to identify and correct errors occurring in the course of transmission that obviates the step of resending the data by the transmitter when errors occur. FEC is implemented by applying an algorithm to a digital data stream to generate redundant bits that are transmitted with the original data. An identical algorithm is performed at the receiver end of the system to compare the transmitted calculation of the encoded data with the received encoding. The result of the comparison is known as the FEC syndrome. A null syndrome is indicative of a received error-free data stream. A non-zero entry in any bit position of the error syndrome must be interpreted to correct one or more errors.
The problem of bit error spreading is compounded further with the presence of FEC at the receiver because the total number of errors in the descrambled data stream may exceed the capability of the FEC decoder. If the error detection and correction capability of the system is exceeded, the original data is corrupted and unrecoverable, and must be retransmitted, thereby impacting overall system performance.
Another factor affecting the correction of scrambled data across a high-speed communications link is the practice of running multiple serial links in a parallel structure. It is becoming more and more common, in order to improve overall system bandwidth, to aggregate multiple links to transmit a packet of data simultaneously over several links or bitlanes. In this manner, the same data payload can be delivered in N/b fraction of the time used for the delivery of a payload over a single link, where N is the time required to transmit one data payload or packet across a single link, and b is the number of links. It is further readily seen that the length of the subdivided packet is also N/b. In theory, N/b could be a fractional number, but in practice, the number of links is chosen in consideration of the packet size (including payload, header and redundant bits), so it is assumed for this example that b divides N evenly, and therefore each sub-packet will contain the same or similar number of bits. In this case, in order to maintain proper bit transition density across each physical link, which is required to achieve a low transmission BER, the dataword is split into b sub-datawords, and each sub-dataword is scrambled and descrambled independently. On the receive side, the decrambled sub-datawords are reconstructed to form the original dataword, which is then decoded for possible error correction.
Certain proposals have been made to provide an ECC compatible with the bit error spreading of a scrambler, such as commonly assigned United States Patent Application US20040193997A1, entitled: “Forward Error Correction Scheme Compatible with the Bit Error Spreading of a Scrambler,” which is incorporated herein by reference. A drawback of such a scheme is that it is not able to correct errors when the packets are transmitted across multiple bitlanes, as mentioned above.
Other applications of FEC codes fail to fully account for the effects of bit error spreading attributable to the descrambling process. For example, a Network Processing Forum paper submitted by Xilinx (NPF 2003.320.00) discloses a 64B/66B encoder that fails to address the bit error multiplication problem caused by descrambling. Another approach has been taken by the Optical Internetworking Forum in document OIF2004.229.03, submitted by PMC-Sierra, Xilinx, and Sandia National Laboratories, which also fails to address the multiplication problem. Similarly, commonly assigned U.S. Patent Application 2004/0193997 A1 discloses a method for combining a simple FEC code with scrambling and descrambling functions to reduce bit error spreading, but requires transmission of data packets over a single serial link and therefore propagates bit error information over multiple packets. Accordingly, a need exists for a FEC code compatible with 64B/66B scrambling format that may be implemented over a multi-channel communication system while preserving channel bandwidth efficiency.